| 1. | Secondly , compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory , a novel topology of cmos preamplifier latch comparator circuit is presented . considering trade - off between kickback noise and power dissipation , reference resistance value is optimized . according to the encode demands of different stage resolution , clock - control encode circuit is designed
其后,在具体的子adc设计中,对比各比较器类型的优缺点,并基于预放大锁存快速比较理论,提出一种新型高速低功耗预放大锁存比较器电路拓扑;根据adc系统所允许的参考电压最大波动限制,在回馈噪声对输入参考电平的影响和功耗之间折衷,确定优化的参考电阻串阻值;根据不同级精度的编码要求,设计出时钟控制编码电路。 |
